Model Based Design
Improved productivity and higher quality for electronic computing systems
More than ever, today’s electronic computing systems are composed of large numbers of interconnected, communicating processes—from the massive web of interconnected compute elements in an FPGA System-On-Chip (SoC), to the multiple cores in a CPU, to the networked elements of a computing cloud. Hardware, software, algorithms, networks, and cyber-physical systems can all be modeled in this way. Implementing these concurrent, often real-time, systems requires the careful design and use of mechanisms to control how the processes communicate as well as how and when they execute (e.g., threads, mutexes, semaphores, hardware signals, enables, clocks, etc.). However, the complexity of such systems can quickly outgrow the capabilities of even the most skilled programmer or team when using these manual techniques. It becomes difficult or impossible to reason about, analyze, validate, verify, or otherwise prove that these systems are free from defects. As a result, creating complex, highly-parallel electronic computing machines suffers from low productivity, low portability, high cost, limited code-reuse, hidden defects, and long development, verification and upgrade cycles.
Benefits of Model Based Design
Model based design methodologies can greatly improve the quality of complex electronic systems while drastically reducing the time required to develop and verify them. The key to successfully leveraging model based methodologies is to select an appropriate level of design abstraction and the proper set of semantic rules for the problem at hand. The level of abstraction should be high enough to improve productivity and the semantic rules expressive enough to model and validate the systems of interest. On the other hand, the level of abstraction should be low enough, and the semantic rules restrictive enough, to enable formal analysis, optimization, and transformation of the model. When these requirements are balanced properly, tools are enabled to generate hardware and software automatically on the target processor(s) of interest (e.g. CPU, DSP, FPGA, GPU). This also allows automatic generation verification tests to demonstrate that the implementation matches the behavior of the validation model.