ParaLea Technology

ParaLea is DSPlogic's high-level, graphical FPGA programming language based upon the Matlab and Simulink platforms. It is an integral part of DSPlogic's Reconfigurable Computing Toolbox.

High-Level FPGA Programming

As a high-level FPGA programming language, ParaLea offers unprecedented productivity. It provides all of the high-level programming constructs that scientists and engineers are accustomed to, such as functions, if-then statements, iterative loops, and switch/case statements. These provide much more efficient and bug-free coding of control logic, typically a stumbling block in many FPGA designs. Innovative multi-port memory access models also simplify programming and increase performance.

Model-based FPGA Programming

ParaLea is fully integrated with Matlab and Simulink. Scientists and engineers can theorize, analyze, visualize, and program FPGA applications in one familiar environment. FPGA program outputs can easily be compared to high-level Matlab/Simulink models for validation.

Xilinx System Generator Integration

ParaLea is fully compatible Xilinx System Generator, which adds a vast amount of IP for rapid algorithm prototyping and development.

Automated Testbench Generation and FPGA Validation

When used in conjunction with a high-level Simulink model, the FPGA program behavior is validated using automatically generated HDL testbenches for Modelsim or other simulator. Behavioral or synthesized modules can be simulated to ensure bit and cycle accurate performance compared with the high-level Simulink model.

Performance Optimized

All programming constructs are optimized for processing speed and throughput. Logic used between clocked registers is kept to a minimum in order to maximize clock speed. This ensures that ParaLea will not slow down the FPGA clock speed achieved by your program. The performance optimization is achieved with only a small increase in resource utilization.

Interfaces

ParaLea easily supports streaming (real-time) or shared-memory data interfaces, as well as simple control interfaces. These interfaces are compatible with common Hardware Abstraction Layers such as Joint Tactical Radio System (JTRS) HAL-C, or OpenFPGA GenAPI.