Power Spectral Density Estimator IP Core

The PSD Estimator FPGA IP Core is a high-performance spectral estimator using Welch's method.  The IP Core is functionally and numerically equivalent to Matlab's PWELCH() command within a normalized accuracy of approximately 10e-5.  The following algorithm parameters are all customizable to optimize performance and/or resource utilization: window length, windowing function, segment overlap, FFT length, number of averages, complex or real-input, and bit widths.  The IP core runs at over 200M Samples/Second on typical Xilinx and Altera devices.  A Matlab model is provided to compare the results of the IP core computation with Matlab's PWELCH() command.

Algorithm

The thorough description of Welch's algorithm is described in detail on the Mathworks website at: www.mathworks.com/access/helpdesk/help/toolbox/signal/pwelch.html

IP Core Entity (Example)

The following is an example of a VHDL entity for the IP core using a streaming data interface.  Shared memory or other interfaces are also available.

   entity psd_est is port (
     clk     : in std_logic;
     reset   : in std_logic;
     iin     : in std_logic_vector(N downto 0);   -- I sample input
     qin     : in std_logic_vector(N downto 0);   -- Q sample input
     iq_en   : in std_logic;                      -- Input sample enable
     psd     : out std_logic)vector(47 downto 0); -- Output PSD
     psd_en  : out std_logic;                     -- Output PSD enable
     psd_bin : out std_logic_vector( 9 downto 0); -- Output Frequency Bin
   end psd_est;