XD1-01: VHDL programming for the Cray XD1

This class will teach you how to accelerate computationally intensive algorithms on the Cray XD1 supercomputer using VHDL programming. General application acceleration strategies will be covered. VHDL design strategies, tools, and validation methods will be discussed. In addition, best practices for modularity, portability, and code re-use will be covered.

Topics include

• Accelerating XD1 Applications using FPGAs
• Suitable applications for acceleration
• Application partitioning
• Host/FPGA communications
• VHDL Programming Flow for the XD1
• Modular design strategies for portability
• Simulating an FPGA program for the XD1
• FPGA clock rate optimization
• Reliable and repeatable FPGA implementations

Prerequisites

• Some VHDL programming ability

Duration

• 1 day

Cost

• $600/person or 6 Training Credits
• Minimum 10 students

Location

• Customer site